1. Field of the Invention
Embodiments of the present invention generally relate to methods for processing semiconductor substrates. More particularly, embodiments of the invention relate to etching openings in dielectric layers on semiconductor substrates.
2. Description of the Related Art
As the structure size of integrated circuit (IC) devices is scaled down to sub-quarter micron dimensions, electrical resistance and current densities have become an area for concern and improvement. Multilevel interconnect technology is used to form high aspect ratio features, including contacts, plugs, vias, lines, wires, and other features. A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more openings, depositing a barrier layer in the openings and depositing one or more layers in the openings to form features. Typically, a conductive feature is formed within a dielectric material disposed between a lower conductive layer and an upper conductive layer to link the upper and lower conductive layers. Reliable formation of these interconnect features is important to the production of the circuits and is instrumental in the continued effort to increase circuit density and quality.
Copper has recently become a choice metal for forming sub-micron, high aspect ratio interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers. For example, such diffusion can form a conductive path between layers, thereby reducing the reliability of the overall circuit and possibly cause device failure.
Barrier layers are deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically contain a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper. To deposit a barrier layer within an interconnect opening, the barrier layer is deposited on the bottom and sidewalls of the opening.
The barrier layers are often deposited on dielectric layers that have been etched to include one or more interconnect openings. The dielectric layers are typically formed of low k (dielectric constant k<4) material. The low k layers may be porous layers.
In addition to preventing the diffusion of metals, such as copper, into a surrounding dielectric layer, barrier layers can also protect the dielectric layer around the sidewalls of a feature from damage from subsequent substrate processing steps, such as wet etching steps. While currently used barrier layers provide some coverage of the sidewalls of the features, there are several problems with the currently used barrier layers. For example, the currently used barrier layers often adhere poorly to low k sidewalls of features, making the layers susceptible to removal from the sidewalls. Also, it can be difficult to deposit the currently used barrier layers conformally on the low k sidewalls. The increasing use of more porous low k materials in the dielectric layers in which the sidewalls are formed has increased both the importance of conformal deposition and the difficulty of conformal deposition, as the pores in the sidewalls provide an irregular surface that has a large surface area that must be covered. Non-conformal layers in a device can contribute to voids in the device and poor device performance.
There is a need, therefore, for processing sequences that provide methods of depositing conformal, well-adhering layers on the sidewalls of interconnect openings in substrates.